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M40Z111 M40Z111W
5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs
FEATURES SUMMARY s CONVERT LOW POWER SRAMs INTO NVRAMs
s
Figure 1. 28-pin SOIC Package
PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION WHEN VCC IS OUT-OF-TOLERANCE CHOICE OF SUPPLY VOLTAGES and POWER-FAIL DESELECT VOLTAGES: - M40Z111: VCC = 4.5 to 5.5V THS = VSS; 4.5 VPFD 4.75V THS = VOUT; 4.2 VPFD 4.5V - M40Z111W: VCC = 3.0 to 3.6V THS = VSS; 2.8 VPFD 3.0V VCC = 2.7 to 3.3V THS = VOUT; 2.5 VPFD 2.7V LESS THAN 15ns CHIP ENABLE ACCESS PROPAGATION DELAY (for 5.0V device) PACKAGING INCLUDES A 28-LEAD SOIC and SNAPHAT(R) TOP (to be ordered separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY
s
SNAPHAT (SH) Battery
s
28 1
SOH28 (MH)
s
s
s
May 2002
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 2.) . . . . . . . Signal Names (Table 1.) . . . . . . . . SOIC28 Connections (Figure 3.) . . Hardware Hookup (Figure 4.) . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....3 .....3 .....3 .....4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC and AC Measurement Conditions (Table 3.) . . . AC Testing Load Circuit (Figure 5.) . . . . . . . . . . . . . Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....5 .....5 .....5 .....6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Down Timing (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Up Timing (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Down/Up AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply Voltage Protection (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Battery Table (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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SUMMARY DESCRIPTION The M40Z111/W NVRAM SUPERVISOR is a selfcontained device which converts a standard lowpower SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the conditioned chip enable (ECON) output is forced inactive to write-protect the stored data in the SRAM. During a power failure, the SRAM is switched from the VCC pin to the lithium cell within the SNAPHAT(R) to provide the energy required for data retention. On a subsequent power-up, the SRAM remains write protected until a valid power condition returns. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is "M4Z28BR00SH" or "M4Z32-BR00SH" (See Table 8, page 10).
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
THS E ECON Threshold Select Input Chip Enable Input Conditioned Chip Enable Output Supply Voltage Output Supply Voltage Ground Not Connected Internally
THS M40Z111 M40Z111W E
VOUT
VOUT VCC
ECON
VSS NC
Figure 3. SOIC28 Connections
VSS
AI02238B
VOUT NC NC NC NC VCC NC VCC NC NC NC NC THS VSS
1 28 27 2 26 3 25 4 24 5 23 6 7 M40Z111 22 8 M40Z111W 21 20 9 19 10 18 11 17 12 16 13 15 14
AI02239B
VCC E NC NC NC NC NC NC NC NC NC NC ECON NC
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Figure 4. Hardware Hookup
3.0, 3.3, or 5V
VCC
VOUT
VCC E2
1N5817 or MBR5120T3
0.1F
0.1F
CMOS SRAM
M40Z111/W E Thereshold THS VSS
ECON
E x8 or x16
AI02394
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TA TSTG TSLD(1) VIO VCC IO PD Output Current Power Dissipation Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value Grade 6 SNAPHAT(R) SOIC -40 to 85 -40 to 85 -55 to 125 260 -0.3 to VCC +0.3 M40Z111 M40Z111W -0.3 to 7.0 -0.3 to 4.6 20 1
Unit C C C C V V V mA W
Note: 1. Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for between 90 to 120 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 3. DC and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Note that Output Hi-Z is defined as the point where data is no longer driven.
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
M40Z111 4.5 to 5.5V -40 to 85C 100pF 5ns 0 to 3V 1.5V
M40Z111W 2.7 to 3.6V -40 to 85C 50pF 5ns 0 to 3V 1.5V
Figure 5. AC Testing Load Circuit
DEVICE UNDER TEST
645
(1) CL = 100pF or 5pF
1.75V
CL includes JIG capacitance
AI02326
Note: 1. 50pF for M40Z111W.
Table 4. Capacitance
Symbol CIN COUT(3) Input Capacitance Output Capacitance Parameter(1,2) Min Max 8 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V (M40Z111) or 3.3V (M40Z111W); sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected
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Table 5. DC Characteristics
Sym ICC ICCDR ILI ILO(2) Parameter Supply Current Data Retention Mode Current Input Leakage Current Output Leakage Current 0V VIN VCC 0V VOUT VCC VOUT > VCC -0.3 VOUT > VCC -0.2 VOUT > VBAT -0.3 2.0 2.2 -0.3 IOH = -2.0mA IOUT2 = -1.0A IOL = 4.0mA VSS 4.50 4.20 4.60 4.35 3.0 2.4 2.0 2.9 3.6 0.4 VOUT 4.75 4.50 VSS 2.80 2.50 2.90 2.60 VPFD - 100mV 100 3.0 3.5 VCC + 0.3 0.8 2.0 2.0 -0.3 2.4 2.0 2.9 3.6 0.4 VOUT 3.00 2.70 Test Condition(1) Outputs open M40Z111 Min Typ 3 Max 6 150 1 1 160 100 100 3.0 3.5 VCC + 0.3 0.8 Min M40Z111W Typ 2 Max 4 150 1 1 100 65 Unit mA nA A A mA mA A V V V V V V V V V V
IOUT1 VOUT Current (Active) IOUT2 VBAT VIH VIL VOH VOHB VOL THS VOUT Current (Battery Back-up) Battery Voltage Input High Voltage Input Low Voltage Output High Voltage VOH Battery Back-up Output Low Voltage Threshold Select Voltage Power-fail Deselect Voltage (THS = VSS) Power-fail Deselect Voltage (THS = VOUT) Battery Back-up Switchover Voltage
VPFD
VSO
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted). 2. Outputs deselected.
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OPERATION The M40Z111/W, as shown in Figure 4, page 4, can control up to two standard low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (ECON) output pin follows the chip enable (E) input pin with timing shown in Table 6, page 9. An internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V (IOUT1). When VCC degrades during a power failure, ECON is forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance threshold (VPFD). The power fail detection value associated with VPFD is selected by the THS pin and is shown in Table 5, page 6. Note: The THS pin must be connected to either VSS or VOUT. If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time tWP, ECON is unconditionally driven high, write protecting the SRAM. A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user can be assured the memory will be write protected provided the VCC fall time exceeds tF. As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT. This occurs at the switchover voltage (VSO ). Below the VSO, the battery provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 5, page 6). When VCC rises
above VSO, VOUT is switched back to the supply voltage. Output ECON is held inactive for tER (200ms maximum) after the power supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure 7, page 8). Data Retention Lifetime Calculation Most low power SRAMs on the market today can be used with the M40Z111/W NVRAM SUPERVISOR. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and SRAMs to be "Don't Care" once VCC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the ICCDR value of the M40Z111/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT(R) of your choice can then be divided by this current to determine the amount of data retention available (see Table 8, page 10). For more information on Battery Storage Life refer to the Application Note AN1012.
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M40Z111, M40Z111W
Figure 6. Power Down Timing
VCC VPFD (max) VPFD VPFD (min)
VSO tF tFB
E tWPT VOHB ECON
AI02396
Figure 7. Power Up Timing
VCC VPFD (max) VPFD VPFD (min)
VSO tR tRB tER E tEDH ECON VOHB tEDL
AI02397
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Table 6. Power Down/Up AC Characteristics
Symbol tF(2) tFB(3) tR tRB tEDL Parameter(1) VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time M40Z111 Chip Enable Propagation Delay M40Z111W M40Z111 tEDH tER(4) tWPT Chip Enable Propagation Delay M40Z111W Chip Enable Recovery M40Z111 Write Protect Time M40Z111W 40 250 s 40 40 20 200 150 ns ms s 20 10 ns ns Min 300 10 10 1 15 Max Unit s s s s ns
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. tER (min) = 20ms for Industrial Temperature Range - Grade 6 device.
VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
Figure 8. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI00622
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M40Z111, M40Z111W
PART NUMBERING Table 7. Ordering Information Scheme
Example: M40Z 111W MH 6 TR
Device Type M40Z
Supply Voltage and Write Protect Voltage 111 = VCC = 4.5 to 5.5V; VPFD = 4.3 to 4.5V THS = VSS = 4.5 VPFD 4.75V THS = VOUT = 4.2 VPFD 4.5V 111W = VCC = 2.7 to 3.6V; VPFD = 2.6 to 2.7V THS = VSS = 2.8 VPFD 3.0V VCC = 2.7 to 3.3V THS = VOUT = 2.5 VPFD 2.7V
Package MH(1) = SOH28
Temperature Range 6 = -40 to 85C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT (R)) which is ordered separately under the part number "M4ZXX-BR00SHX" in plastic tube or "M4ZXX-BR00SHXTR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery package "M4ZXX-BR00SH" in conductive foam as this will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 8. Battery Table
Part Number M4Z28-BR00SH M4Z32-BR00SH Description SNAPHAT Housing for 48mAh Battery SNAPHAT Housing for 120mAh Battery Package SH SH
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M40Z111, M40Z111W
PACKAGE MECHANICAL INFORMATION Figure 9. SOH28 - 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note: Drawing is not to scale.
Table 9. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
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Figure 10. 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note: Drawing is not to scale.
Table 10. 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
mm Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
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Figure 11. 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note: Drawing is not to scale.
Table 11. 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
mm Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090 inches
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REVISION HISTORY Table 12. Document Revision History
Date September 2000 09/14/01 05/13/02 First Draft Issue Reformatted, TOC added, changed DC Characteristics (Table 5); changed battery, ind. temperature information (Tables 2, 6, 7, 8, Figures 10, 11); Corrected SOIC label (Figure 3); added E2 to Hookup (Figure 4) Modify reflow time and temperature footnote (Table 2) Revision Details
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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